1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a non-volatile semiconductor storage element and a resistance element.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) which is a non-volatile semiconductor storage device has a memory cell having an metal insulator semiconductor field effect transistor (MISFET) structure in which a charge storage layer (a floating gate electrode) and a control gate electrode are laminated above a semiconductor substrate. This memory cell stores data in a non-volatile manner by using a difference in threshold voltage of FET between states in which electronic charge is injected into the charge storage layer and the electronic charge is extracted therefrom. Injection/extraction of the electronic charge is controlled by tunneling current which passes through a tunnel insulator provided between the charge storage layer and a channel being formed in the substrate. Among various types of EEPROMs, a so-called NAND type EEPROM is advantageous to higher integration since the number of select transistors can be reduced as compared with an NOR type EEPROM. The NAND type EEPROM connects a plurality of memory cells in series to constitute an NAND cell unit.
In the NOR type flash memory, data is also erased by flowing tunneling current through the tunnel insulator between the charge storage layer and the channel in the substrate so that the erase operation can be hardly affected by a short channel effect. For example, a plurality of memory cells is simultaneously erased data so that the number of memory cells being erased data in a given time is increased. Therefore, electrons are extracted from the charge storage layer to the substrate by applying a high voltage, which is not smaller than 10V, e.g., a positive voltage of 20V, to a well formed in the semiconductor substrate where the memory cells are formed. On the other hand, when writing data, a well voltage is maintained at 0V, and a positive voltage, which is not smaller than 10V, is applied to a source/drain of the memory cell having a smaller charging/discharging capacitance than that of the well. Since the charging/discharging capacitance of the memory cell is smaller than that of the well, an electric power which charges/discharges the well can be reduced, thereby increasing an operating speed.
In order to allow such an operation, in the NAND-connected memory cells, variation in threshold voltage of non-selected memory cells connected to selected memory cells in series must be sufficiently lowered, and variations in current in a reading operation of the selected memory cells must be reduced. Thus, the positive voltage must be controlled within a variation of 0.5V or less in order to maintain a distribution of the threshold voltage after writing to be narrow and reduce variations in threshold voltage among chips.
Further, in a conventional non-volatile semiconductor storage device, an erase operation, a write operation and a read operation of the non-volatile memory cells are switched by using a signal supplied externally. Therefore, there are required a logical peripheral circuit to change a voltage applied to a well, where memory cells are formed, from the external input and a logical peripheral circuit to output data read from memory cells to the outside. Each of these circuits is constituted of a CMOS circuit in order to reduce power consumption, and uses a voltage of not greater than 5V, e.g., 3.3V or 1.8V as an input/output voltage from/to the outside. This voltage is greatly lower than the voltage of 10V or above required in the write operation or the erase operation.
Thus, in order to perform a feedback control over the positive voltage by the logical peripheral circuit, there is employed, e.g., a method of converting a voltage of 10V or higher into a lower voltage by resistance division. In this case, in a resistance element used for resistance division, a higher resistance is preferable since it can reduce a current flowing through the resistance element and thus reduce a consumed power.
Conventionally, the resistance element is formed by a method, for example, disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2002-110825. A polycrystal silicon which serves as a floating gate electrode is deposited on an entire surface of a semiconductor substrate via a tunnel insulator and then processed by lithography and etching, thereby forming a trench for isolation in the polysilicon and substrate. Then, a thick isolation insulator is deposited to form an isolation. Subsequently, polycrystal silicon which serves as a control gate electrode is deposited on an entire surface and processed by lithography and etching, thereby the control gate electrode and the resistance element are formed from the same material. As to this lithography, since a processing dimension is relatively loose, an less expensive lithography having a lower resolution and lower accuracy can be used. However, when such lithography is used, there occurs a problem that a line width of a stripe-shaped area of the polycrystal silicon, which serves as the resistance element, cannot be finely formed and a variation in the width becomes large. As a result, when obtaining a high resistance, there occurs a problem such as an increased chip size due to increase in the stripe-shaped polycrystal silicon area being formed the high resistance element. Furthermore, if the variation in the width is large, then a relative resistance variation becomes large, thus a larger margin in timing must be required if the resistance element is used in a timing generation circuit of a circuitry.
In another example, as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-85617, there is a technique by which a gate electrode of MOSFET and a resistance element are formed of the same material. In this technique, an isolation is first formed in a semiconductor substrate. Then polycrystal silicon to which a gate electrode is being formed is deposited on an entire surface of the semiconductor substrate via a gate insulator and processed by lithography and etching to form the resistance element and the gate electrode from the same material, simultaneously.
In each of the above-described conventional techniques, an additional lithography to form the resistance element different from the lithography for the isolation is required, thus the number of the lithography steps is increased, which leads to an increase in a manufacturing process cost.
Therefore, there is a need for rationally realizing a semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element even if design rule is shrunk.